The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for forming inner spacers and reducing contact resistance in vertically stacked nanosheet transistors.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as silicon channel n-type field effect transistors (nFETs) and silicon germanium channel p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as nanosheet (or nanowire) transistors, can provide increased device density and increased performance over planar transistors. Nanosheet transistors, in contrast to conventional planar FETs, include a gate stack that wraps around the full perimeter of multiple nanosheet channel regions. Nanosheet transistor configurations enable fuller depletion in the nanosheet channel regions and reduce short-channel effects.